Command Processor (CP)
The command processor (CP) is responsible for fetching and processing GX commands generated by the CPU from an in-memory ring buffer (FIFO).
Registers
All FIFO registers are middle endian.
CP Status (0x0C00_0000, 2 bytes)
Contains status regarding the command processor.
| Bits | Name | Description |
|---|---|---|
| 0 | CP FIFO Overflow | Watermark logic |
| 1 | CP FIFO Underflow | Watermark logic |
| 2 | CP read idle | |
| 3 | CP command idle | |
| 4 | Breakpoint Interrupt | |
| 5..16 | Unused |
CP Control (0x0C00_0002, 2 bytes)
Controls the command processor.
| Bits | Name | Description |
|---|---|---|
| 0 | CP FIFO Read Enable | Whether the CP will read commands from the FIFO |
| 1 | CP FIFO Breakpoint Enable | |
| 2 | CP FIFO Overflow IRQ Enable | |
| 3 | CP FIFO Underflow IRQ Enable | |
| 4 | CP FIFO Linked Mode | Controls the FIFO mode. Is set on reset. |
| 5 | CP FIFO Breakpoint IRQ Enable | |
| 6..16 | Unused |
CP Clear (0x0C00_0004, 2 bytes, write only)
| Bits | Name | Description |
|---|---|---|
| 0 | Clear CP FIFO Overflow | Write 1 to clear status bit 0 |
| 1 | Clear CP FIFO Underflow | Write 1 to clear status bit 1 |
| 2..16 | Unused |
CP FIFO Start (0x0C00_0020, 4 bytes)
Start address of the ring buffer.
CP FIFO End (0x0C00_0024, 4 bytes)
End address of the ring buffer (exclusive).
CP FIFO High Watermark (0x0C00_0028, 4 bytes)
Ring buffer’s high watermark, i.e. the remaining capacity of the CP FIFO that triggers a high watermark interrupt.
CP FIFO Low Watermark (0x0C00_002C, 4 bytes)
Ring buffer’s low watermark, i.e. the remaining capacity of the CP FIFO that triggers a low watermark interrupt.
CP FIFO Count (0x0C00_0030, 4 bytes)
Distance between the FIFO read and write pointers.
CP FIFO Write Pointer (0x0C00_0034, 4 bytes)
Current address of the FIFO write pointer (i.e. where new data is going to be written).
CP FIFO Read Pointer (`0x0C00_00348, 4 bytes)
Current address of the FIFO read pointer (i.e. where new data is going to read from).